Today's computer chips are increasingly dependent on robust memory architecture capable of quickly accessing and handling large amounts of data. Existing memory solutions such as off-chip physical dynamic random access memory (DRAM) that sit on the mother board separate from the computer chip require relatively large amounts of energy and suffer from high latency, resulting in power-performance loss. Latency problems have been addressed using 1T-1C Dynamic Random Access Memory (“DRAM”) cells that have a transistor and a capacitor that are embedded on the computer chip. Existing versions of such DRAM cells, however, are frequently unable to meet ever-increasing capacitance demands.